662 lines
14 KiB
C++
662 lines
14 KiB
C++
#include "daisy.h"
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#include "audioc.hpp"
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#include "tft.hpp"
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using namespace daisy;
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static tft_cmd init_cmds[] = {
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tft_cmd(0xEF, {0x03, 0x80, 0x02}),
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tft_cmd(0xCF, {0x00, 0xC1, 0x30}),
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tft_cmd(0xED, {0x64, 0x03, 0x12, 0x81}),
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tft_cmd(0xE8, {0x85, 0x00, 0x78}),
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tft_cmd(0xCB, {0x39, 0x2C, 0x00, 0x34, 0x02}),
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tft_cmd(0xF7, {0x20}),
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tft_cmd(0xEA, {0x00, 0x00}),
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tft_cmd(ILI9341_PWCTR1, {0x23}), // Power control VRH[5:0]
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tft_cmd(ILI9341_PWCTR2, {0x10}), // Power control SAP[2:0];BT[3:0]
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tft_cmd(ILI9341_VMCTR1, {0x3e, 0x28}), // VCM control
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tft_cmd(ILI9341_VMCTR2, {0x86}), // VCM control2
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tft_cmd(ILI9341_MADCTL, {0x08}), // Memory Access Control
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tft_cmd(ILI9341_VSCRSADD, {0x00}), // Vertical scroll zero
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tft_cmd(ILI9341_PIXFMT, {0x55}), // 16 bit pixel fmt
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tft_cmd(ILI9341_FRMCTR1, {0x00, 0x18}),
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tft_cmd(ILI9341_DFUNCTR, {0x08, 0x82, 0x27}), // Display Function Control
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tft_cmd(0xF2, {0x00}), // 3Gamma Function Disable
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tft_cmd(ILI9341_GAMMASET, {0x01}), // Gamma curve selected
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tft_cmd(ILI9341_GMCTRP1, {0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, // Set Gamma
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0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00}),
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tft_cmd(ILI9341_GMCTRN1, {0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, // Set Gamma
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0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F}),
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tft_cmd(ILI9341_SLPOUT, 150), // Exit Sleep
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tft_cmd(ILI9341_DISPON, 150), // Display on
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};
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static tft_cmd RESET_CMD(ILI9341_SWRESET, 150);
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int
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tft_driver_ili9341::init(uint8_t *dma_buf, size_t dma_sz)
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{
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AC_PRECOND(_async_stat == async_status::INIT);
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SpiHandle::Result res;
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dcx_pin = daisy::seed::D12; // Pin(PORTB, 8);
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dcx.Init(dcx_pin, GPIO::Mode::OUTPUT, GPIO::Pull::NOPULL,
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GPIO::Speed::HIGH);
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spi_conf.datasize = 8;
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spi_conf.mode = SpiHandle::Config::Mode::MASTER;
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spi_conf.direction = SpiHandle::Config::Direction::TWO_LINES;
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spi_conf.clock_polarity = SpiHandle::Config::ClockPolarity::LOW;
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spi_conf.clock_phase = SpiHandle::Config::ClockPhase::ONE_EDGE;
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spi_conf.baud_prescaler = SpiHandle::Config::BaudPrescaler::PS_2;
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spi_conf.periph = SpiHandle::Config::Peripheral::SPI_1;
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spi_conf.nss = SpiHandle::Config::NSS::HARD_OUTPUT;
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spi_conf.pin_config.nss = daisy::seed::D7; //Pin(PORTG, 10); // D7
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spi_conf.pin_config.sclk = daisy::seed::D8; //Pin(PORTG, 11); // D8
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spi_conf.pin_config.miso = daisy::seed::D9; // Pin(PORTB, 4); // D9
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spi_conf.pin_config.mosi = daisy::seed::D10; //Pin(PORTB, 5); // D10
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res = spi.Init(spi_conf);
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if (res == SpiHandle::Result::ERR)
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return (-1);
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daisy_hw.PrintLine("resetting tft");
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send_sync(&RESET_CMD);
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for (auto cmd : init_cmds) {
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daisy_hw.PrintLine("sending tft init command");
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send_sync(&cmd);
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}
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_async_dma_buf = dma_buf;
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_async_dma_sz = dma_sz;
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_async_curr_rd = _async_curr_wr = (tft_dma_cmd *)dma_buf;
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_async_id = 0;
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_async_stat = async_status::INIT;
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return (0);
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}
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void
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tft_driver_ili9341::set_addr_window(uint16_t col_st, uint16_t width,
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uint16_t row_st, uint16_t height)
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{
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uint16_t start, end;
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start = col_st; end = col_st + width;
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tft_cmd col_set(ILI9341_CASET,
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{ (uint8_t)((start >> 8) & 0xff), (uint8_t)(start & 0xff),
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(uint8_t)((end >> 8) & 0xff), (uint8_t)(end & 0xff) });
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start = row_st; end = row_st + height;
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tft_cmd row_set(ILI9341_PASET,
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{ (uint8_t)((start >> 8) & 0xff), (uint8_t)(start & 0xff),
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(uint8_t)((end >> 8) & 0xff), (uint8_t)(end & 0xff) });
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send_sync(&col_set);
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send_sync(&row_set);
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}
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void
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tft_driver_ili9341::async_on_finish(async_on_finish_f cb, void *ctx)
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{
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_async_cb_fun = cb;
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_async_cb_ctx = ctx;
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}
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int
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tft_driver_ili9341::async_ready(void)
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{
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async_status stat;
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stat = (async_status)_async_stat;
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switch (stat) {
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case async_status::INIT:
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case async_status::DONE:
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if (_async_cb_fun == NULL ||
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_async_cb_ctx == NULL ||
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_async_id < 0)
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return (-1);
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_async_stat = async_status::READY;
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__attribute__((fallthrough));
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case async_status::READY:
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return (0);
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default:
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break;
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}
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return (-1);
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}
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int
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tft_driver_ili9341::dma_buf_reset(void)
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{
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async_status stat;
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tft_dma_cmd *cmd;
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if (dma_buf_sz_tx_pend() > 0)
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return (-1);
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stat = _async_stat;
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switch (stat) {
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case async_status::INIT:
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case async_status::TX_NONE:
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case async_status::TX_ACTIVE:
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return (-1);
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default:
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break;
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}
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cmd = (tft_dma_cmd *)_async_dma_buf;
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cmd->size = 0;
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_async_curr_wr = cmd;
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_async_curr_rd = cmd;
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return (0);
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}
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int
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tft_driver_ili9341::async_start(void)
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{
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if (async_ready() == -1)
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return (-1);
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if (dma_buf_reset() == -1)
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return (-1);
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_async_wr = async_wr::START;
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_async_stat = async_status::TX_NONE;
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return (async_id());
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}
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int
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tft_driver_ili9341::async_end(void)
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{
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_async_wr = async_wr::END;
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async_id_next();
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async_flush();
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return (0);
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}
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tft_driver_ili9341::async_status
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tft_driver_ili9341::async_stat(void)
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{
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return (_async_stat);
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}
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void
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tft_driver_ili9341::async_finalize(void)
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{
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AC_PRECOND(_async_cb_fun != NULL && _async_cb_ctx != NULL);
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AC_PRECOND(_async_stat == async_status::TX_NONE ||
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_async_stat == async_status::TX_INACTIVE ||
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_async_stat == async_status::TX_ACTIVE);
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AC_PRECOND(_async_wr == async_wr::END);
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AC_PRECOND(dma_buf_sz_tx_pend() == 0);
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_async_stat = async_status::DONE;
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_async_cb_fun((void *)_async_cb_ctx);
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}
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void
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tft_driver_ili9341::async_flush(void)
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{
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async_status stat;
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async_wr wr;
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stat = _async_stat;
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wr = _async_wr;
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switch (stat) {
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case async_status::TX_NONE:
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case async_status::TX_INACTIVE:
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if (dma_buf_sz_tx_pend() > 0) {
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async_tx();
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return;
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}
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if (wr == async_wr::END) {
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async_finalize();
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return;
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}
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dma_buf_reset();
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break;
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default:
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break;
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}
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}
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#define TFT_ASYNC_TRY_TX_MIN 2048
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void
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tft_driver_ili9341::async_tx_try(void)
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{
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if (dma_buf_sz_tx_pend() < (_async_dma_sz / 2))
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return;
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async_flush();
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}
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void
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tft_driver_ili9341::async_tx(void)
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{
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async_status stat;
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stat = _async_stat;
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AC_ASSERT(stat == async_status::TX_NONE ||
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stat == async_status::TX_INACTIVE);
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AC_ASSERT(dma_buf_sz_tx_pend() > sizeof(tft_dma_cmd));
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AC_ASSERT(_async_curr_rd->size > 0);
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_async_stat = async_status::TX_ACTIVE;
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async_send_raw((const uint8_t *)_async_curr_rd->buf, 1,
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async_tx_cmd_scb, async_tx_cmd_ecb, this);
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}
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/* ret < 0: if error
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* ret = 0: if success
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* ret > 0: need reentrant call, ret == async_id that should be used in next
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* call
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*/
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int
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tft_driver_ili9341::async_hline_row_bg_fill(int id, tft_color *bg,
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tft_color *fg, uint16_t hline_idx_st, uint16_t hline_idx_end,
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uint16_t row_idx)
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{
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int ret;
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if (id != _async_id)
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return (-1);
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ret = render_dma_buf_hline_row_bg_fill(bg, fg, hline_idx_st,
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hline_idx_end, row_idx);
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if (ret < 0)
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return (ret);
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if (ret > 0)
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async_flush();
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async_tx_try();
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return (ret);
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}
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void
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tft_driver_ili9341::async_tx_cmd_scb(void *ctx)
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{
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tft_driver_ili9341 *tft;
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tft = (tft_driver_ili9341 *)ctx;
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AC_ASSERT(tft->_async_stat == async_status::TX_ACTIVE);
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tft->dcx_low();
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}
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void
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tft_driver_ili9341::async_tx_cmd_ecb(void *ctx, SpiHandle::Result res)
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{
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tft_driver_ili9341 *tft;
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const tft_dma_cmd *cmd;
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tft = (tft_driver_ili9341 *)ctx;
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cmd = tft->dma_buf_curr_rd();
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AC_ASSERT(tft->_async_stat == async_status::TX_ACTIVE);
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tft->async_send_raw(&cmd->buf[1], cmd->size, async_tx_param_scb,
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async_tx_param_ecb, tft);
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}
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void
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tft_driver_ili9341::async_tx_param_scb(void *ctx)
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{
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tft_driver_ili9341 *tft;
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tft = (tft_driver_ili9341 *)ctx;
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AC_ASSERT(tft->_async_stat == async_status::TX_ACTIVE);
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tft->dcx_high();
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}
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void
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tft_driver_ili9341::async_tx_param_ecb(void *ctx, SpiHandle::Result res)
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{
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tft_driver_ili9341 *tft;
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const tft_dma_cmd *cmd;
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tft = (tft_driver_ili9341 *)ctx;
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AC_PRECOND(tft->_async_stat == async_status::TX_ACTIVE);
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cmd = tft->dma_buf_next_rd();
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if (cmd->size == 0) {
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if (tft->_async_wr == async_wr::END) {
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AC_ASSERT(tft->dma_buf_sz_tx_pend() == 0);
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tft->async_finalize();
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} else {
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tft->_async_stat = async_status::TX_INACTIVE;
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}
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return;
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}
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AC_ASSERT(tft->dma_buf_sz_tx_pend() > sizeof(tft_dma_cmd));
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tft->async_send_raw(cmd->buf, 1, async_tx_cmd_scb, async_tx_cmd_ecb,
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tft);
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}
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size_t
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tft_driver_ili9341::dma_buf_sz_tx_pend(void)
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{
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return ((size_t)
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((uint8_t *)_async_curr_wr - (uint8_t *)_async_curr_rd));
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}
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size_t
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tft_driver_ili9341::dma_buf_sz_used(void)
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{
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size_t buf_fill;
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buf_fill = (size_t)((uint8_t *)_async_curr_wr - _async_dma_buf) +
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sizeof(tft_dma_cmd);
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return (buf_fill);
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}
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tft_dma_cmd *
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tft_driver_ili9341::dma_buf_curr_wr(void)
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{
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return ((tft_dma_cmd *)_async_curr_wr);
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}
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tft_dma_cmd *
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tft_driver_ili9341::dma_buf_next_wr(size_t curr_sz)
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{
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size_t tot_sz;
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volatile tft_dma_cmd *curr, *next;
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volatile uint8_t *bytes;
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AC_PRECOND(_async_dma_sz - dma_buf_sz_used() >=
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curr_sz + sizeof(tft_dma_cmd));
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curr = (volatile tft_dma_cmd *)_async_curr_wr;
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tot_sz = sizeof(*curr) + curr_sz;
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bytes = (volatile uint8_t *)curr;
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bytes += tot_sz;
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next = (volatile tft_dma_cmd *)bytes;
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next->size = 0;
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curr->size = curr_sz;
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_async_curr_wr = next;
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return ((tft_dma_cmd *)next);
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}
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const tft_dma_cmd *
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tft_driver_ili9341::dma_buf_curr_rd(void)
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{
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return ((const tft_dma_cmd *)_async_curr_rd);
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}
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const tft_dma_cmd *
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tft_driver_ili9341::dma_buf_next_rd(void)
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{
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size_t sz;
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volatile const tft_dma_cmd *cmd;
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volatile const uint8_t *bytes;
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cmd = (volatile const tft_dma_cmd *)_async_curr_rd;
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sz = sizeof(*cmd) + cmd->size;
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bytes = (volatile const uint8_t *)cmd;
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bytes += sz;
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cmd = (volatile const tft_dma_cmd *)bytes;
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_async_curr_rd = cmd;
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return ((const tft_dma_cmd *)cmd);
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}
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#define SET_ADDR_WINDOW_SZ (sizeof(tft_dma_cmd) + 5 + \
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sizeof(tft_dma_cmd) + 5)
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int
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tft_driver_ili9341::render_dma_buf_set_addr_window(uint16_t col_st,
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uint16_t col_end, uint16_t row_st, uint16_t row_end)
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{
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size_t n;
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tft_dma_cmd *cmd;
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if (_async_dma_sz - dma_buf_sz_used() < SET_ADDR_WINDOW_SZ)
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return (1);
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cmd = dma_buf_curr_wr();
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n = 0;
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cmd->buf[n++] = ILI9341_CASET;
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cmd->buf[n++] = (uint8_t)((col_st >> 8) & 0xff);
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cmd->buf[n++] = (uint8_t)(col_st & 0xff);
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cmd->buf[n++] = (uint8_t)((col_end >> 8) & 0xff);
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cmd->buf[n++] = (uint8_t)(col_end & 0xff);
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cmd = dma_buf_next_wr(n);
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n = 0;
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cmd->buf[n++] = ILI9341_PASET;
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cmd->buf[n++] = (uint8_t)((row_st >> 8) & 0xff);
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cmd->buf[n++] = (uint8_t)(row_st & 0xff);
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cmd->buf[n++] = (uint8_t)((row_end >> 8) & 0xff);
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cmd->buf[n++] = (uint8_t)(row_end & 0xff);
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dma_buf_next_wr(n);
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return (0);
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}
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#define MEMWR_SZ(num) (sizeof(tft_dma_cmd) + 1 + (num) * sizeof(uint16_t))
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int
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tft_driver_ili9341::render_dma_buf_memwr(const tft_color *col, size_t num)
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{
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size_t i, n;
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uint16_t c16;
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tft_dma_cmd *cmd;
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if (_async_dma_sz - dma_buf_sz_used() < MEMWR_SZ(num))
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return (1);
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cmd = dma_buf_curr_wr();
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c16 = col->u16();
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i = 0;
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cmd->buf[i++] = ILI9341_RAMWR;
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for (n = 0; n < num; n++) {
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cmd->buf[i++] = (uint8_t)((c16 >> 8) & 0xff);
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cmd->buf[i++] = (uint8_t)(c16 & 0xff);
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}
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dma_buf_next_wr(i);
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return (0);
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}
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|
#define MEMWR_CONT_SZ(num) MEMWR_SZ(num)
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int
|
|
tft_driver_ili9341::render_dma_buf_memwr_cont(const tft_color *col, size_t num)
|
|
{
|
|
size_t i, n;
|
|
uint16_t c16;
|
|
tft_dma_cmd *cmd;
|
|
|
|
if (_async_dma_sz - dma_buf_sz_used() < MEMWR_CONT_SZ(num)) {
|
|
return (1);
|
|
}
|
|
|
|
cmd = dma_buf_curr_wr();
|
|
|
|
c16 = col->u16();
|
|
i = 0;
|
|
cmd->buf[i++] = ILI9341_WRCONT;
|
|
for (n = 0; n < num; n++) {
|
|
cmd->buf[i++] = (uint8_t)((c16 >> 8) & 0xff);
|
|
cmd->buf[i++] = (uint8_t)(c16 & 0xff);
|
|
}
|
|
|
|
dma_buf_next_wr(i);
|
|
|
|
return (0);
|
|
}
|
|
|
|
|
|
int
|
|
tft_driver_ili9341::render_dma_buf_hline(const tft_color *c, uint16_t col_s,
|
|
uint16_t col_e, uint16_t row)
|
|
{
|
|
int ret;
|
|
|
|
AC_PRECOND(col_s <= col_e);
|
|
|
|
if (_async_dma_sz - dma_buf_sz_used() <
|
|
SET_ADDR_WINDOW_SZ + MEMWR_SZ(col_e - col_s))
|
|
return (1);
|
|
|
|
ret = render_dma_buf_set_addr_window(col_s, col_e, row, row + 1);
|
|
if (ret != 0)
|
|
return (ret);
|
|
|
|
ret = render_dma_buf_memwr(c, (size_t)(col_e - col_s));
|
|
|
|
return (ret);
|
|
}
|
|
|
|
int
|
|
tft_driver_ili9341::render_dma_buf_hline_row_bg_fill(const tft_color *bg,
|
|
const tft_color *fg, uint16_t col_s, uint16_t col_e, uint16_t row)
|
|
{
|
|
int ret;
|
|
|
|
AC_PRECOND(col_s <= col_s && col_e <= width());
|
|
|
|
if (_async_dma_sz - dma_buf_sz_used() <
|
|
SET_ADDR_WINDOW_SZ + MEMWR_SZ(col_s) + MEMWR_CONT_SZ(col_e - col_s))
|
|
return (1);
|
|
|
|
ret = render_dma_buf_set_addr_window(0, width(), row, row+1);
|
|
if (ret != 0)
|
|
return (ret);
|
|
|
|
ret = render_dma_buf_memwr(bg, (size_t)col_s);
|
|
if (ret != 0)
|
|
return (ret);
|
|
|
|
ret = render_dma_buf_memwr_cont(fg, (size_t)(col_e - col_s));
|
|
if (ret != 0)
|
|
return (ret);
|
|
|
|
ret = render_dma_buf_memwr_cont(bg, (size_t)(width() - col_e));
|
|
|
|
return (ret);
|
|
}
|
|
|
|
#define TFT_N_PIXELS (ILI9341_TFTWIDTH * ILI9341_TFTHEIGHT)
|
|
#define TFT_BLOCK_SZ ((size_t)16386)
|
|
int
|
|
tft_driver_ili9341::fill_screen(const tft_color *c)
|
|
{
|
|
uint8_t buf[TFT_BLOCK_SZ];
|
|
size_t n, i;
|
|
uint16_t c16;
|
|
|
|
set_addr_window(0, width(), 0, height());
|
|
if (send_sync(ILI9341_RAMWR, NULL, 0) == -1)
|
|
return (-1);
|
|
|
|
i = 0;
|
|
c16 = c->u16();
|
|
for (n = 0; n < sizeof(buf) / sizeof(uint16_t); n++) {
|
|
buf[i++] = (uint8_t)((c16 >> 8) & 0xff);
|
|
buf[i++] = (uint8_t)(c16 & 0xff);
|
|
}
|
|
|
|
for (n = 0;
|
|
n < TFT_N_PIXELS * sizeof(uint16_t);
|
|
n += i) {
|
|
if (send_raw_sync(buf,
|
|
std::min(i, (TFT_N_PIXELS * sizeof(uint16_t)) - n)) == -1)
|
|
return (-1);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
tft_driver_ili9341::send_sync(const tft_cmd *cmd)
|
|
{
|
|
if (send_sync(cmd->cmd, cmd->param_bytes(), cmd->param_len) == -1)
|
|
return (-1);
|
|
|
|
if (cmd->post_delay > 0)
|
|
System::Delay(cmd->post_delay);
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
tft_driver_ili9341::send_sync(uint8_t cmd, const uint8_t *buf, size_t len)
|
|
{
|
|
SpiHandle::Result res;
|
|
|
|
dcx_low();
|
|
res = spi.BlockingTransmit(&cmd, 1);
|
|
dcx_high();
|
|
|
|
if (res == SpiHandle::Result::ERR)
|
|
return (-1);
|
|
|
|
if (len == 0)
|
|
return (0);
|
|
|
|
res = spi.BlockingTransmit((uint8_t *)buf, len);
|
|
|
|
return (res == SpiHandle::Result::ERR ? -1 : 0);
|
|
}
|
|
|
|
int
|
|
tft_driver_ili9341::send_raw_sync(const uint8_t *buf, size_t len)
|
|
{
|
|
size_t block_st, transfer_sz;
|
|
SpiHandle::Result res;
|
|
|
|
res = SpiHandle::Result::OK;
|
|
for (block_st = 0; block_st < len; block_st += TFT_BLOCK_SZ) {
|
|
transfer_sz = std::min(TFT_BLOCK_SZ, len - block_st);
|
|
res = spi.BlockingTransmit((uint8_t *)&buf[block_st],
|
|
transfer_sz);
|
|
}
|
|
|
|
return (res == SpiHandle::Result::ERR ? -1 : 0);
|
|
}
|
|
|